119 lines
3.7 KiB
C++
119 lines
3.7 KiB
C++
/*
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* Copyright (c) 2011, 2012, 2013, 2014 Jonas 'Sortie' Termansen.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* x86-family/pic.cpp
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* Driver for the Programmable Interrupt Controller.
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*/
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#include <stdint.h>
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#include <sortix/kernel/cpu.h>
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#include <sortix/kernel/interrupt.h>
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#include <sortix/kernel/ioport.h>
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#include <sortix/kernel/kernel.h>
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#include "pic.h"
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namespace Sortix {
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namespace PIC {
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const uint16_t PIC_MASTER = 0x20;
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const uint16_t PIC_SLAVE = 0xA0;
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const uint16_t PIC_COMMAND = 0x00;
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const uint16_t PIC_DATA = 0x01;
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const uint8_t PIC_CMD_ENDINTR = 0x20;
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const uint8_t PIC_ICW1_ICW4 = 0x01; // ICW4 (not) needed
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const uint8_t PIC_ICW1_SINGLE = 0x02; // Single (cascade) mode
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const uint8_t PIC_ICW1_INTERVAL4 = 0x04; // Call address interval 4 (8)
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const uint8_t PIC_ICW1_LEVEL = 0x08; // Level triggered (edge) mode
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const uint8_t PIC_CMD_INIT = 0x10;
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const uint8_t PIC_MODE_8086 = 0x01; // 8086/88 (MCS-80/85) mode
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const uint8_t PIC_MODE_AUTO = 0x02; // Auto (normal) EOI
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const uint8_t PIC_MODE_BUF_SLAVE = 0x08; // Buffered mode/slave
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const uint8_t PIC_MODE_BUF_MASTER = 0x0C; // Buffered mode/master
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const uint8_t PIC_MODE_SFNM = 0x10; // Special fully nested (not)
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const uint8_t PIC_READ_IRR = 0x0A;
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const uint8_t PIC_READ_ISR = 0x0B;
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static uint16_t ReadRegister(uint8_t ocw3)
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{
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outport8(PIC_MASTER + PIC_COMMAND, ocw3);
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outport8(PIC_SLAVE + PIC_COMMAND, ocw3);
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return inport8(PIC_MASTER + PIC_COMMAND) << 0 |
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inport8(PIC_SLAVE + PIC_COMMAND) << 8;
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}
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uint16_t ReadIRR()
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{
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return ReadRegister(PIC_READ_IRR);
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}
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uint16_t ReadISR()
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{
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return ReadRegister(PIC_READ_ISR);
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}
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extern "C" void ReprogramPIC()
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{
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uint8_t master_mask = 0;
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uint8_t slave_mask = 0;
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outport8(PIC_MASTER + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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outport8(PIC_SLAVE + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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outport8(PIC_MASTER + PIC_DATA, Interrupt::IRQ0);
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outport8(PIC_SLAVE + PIC_DATA, Interrupt::IRQ8);
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outport8(PIC_MASTER + PIC_DATA, 0x04); // Slave PIC at IRQ2
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outport8(PIC_SLAVE + PIC_DATA, 0x02); // Cascade Identity
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outport8(PIC_MASTER + PIC_DATA, PIC_MODE_8086);
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outport8(PIC_SLAVE + PIC_DATA, PIC_MODE_8086);
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outport8(PIC_MASTER + PIC_DATA, master_mask);
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outport8(PIC_SLAVE + PIC_DATA, slave_mask);
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}
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extern "C" void DeprogramPIC()
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{
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uint8_t master_mask = 0;
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uint8_t slave_mask = 0;
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outport8(PIC_MASTER + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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outport8(PIC_SLAVE + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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outport8(PIC_MASTER + PIC_DATA, 0x08);
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outport8(PIC_SLAVE + PIC_DATA, 0x70);
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outport8(PIC_MASTER + PIC_DATA, 0x04); // Slave PIC at IRQ2
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outport8(PIC_SLAVE + PIC_DATA, 0x02); // Cascade Identity
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outport8(PIC_MASTER + PIC_DATA, PIC_MODE_8086);
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outport8(PIC_SLAVE + PIC_DATA, PIC_MODE_8086);
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outport8(PIC_MASTER + PIC_DATA, master_mask);
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outport8(PIC_SLAVE + PIC_DATA, slave_mask);
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}
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void SendMasterEOI()
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{
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outport8(PIC_MASTER, PIC_CMD_ENDINTR);
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}
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void SendSlaveEOI()
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{
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outport8(PIC_SLAVE, PIC_CMD_ENDINTR);
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}
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void SendEOI(unsigned int irq)
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{
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if ( 8 <= irq )
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SendSlaveEOI();
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SendMasterEOI();
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}
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} // namespace PIC
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} // namespace Sortix
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