This provides control over the caching of memory, which makes write-combined IO possible. Graphics drivers can use this to transfer data at a much higher rate to the video memory. The implementation is a bit hacky but it'll do for now. It provides enough support for the experimental VBE driver to work on the real computers I tested it on, even if the BIOS uses screwed up default MTRRs. The virtual memory layer now automatically uses the PAT feature if available but in a backwards compatible manner and otherwise just tries to approximate PAT features if they are asked for.
103 lines
2.8 KiB
C++
103 lines
2.8 KiB
C++
/******************************************************************************
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COPYRIGHT(C) JONAS 'SORTIE' TERMANSEN 2011.
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This file is part of Sortix.
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Sortix is free software: you can redistribute it and/or modify it under the
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terms of the GNU General Public License as published by the Free Software
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Foundation, either version 3 of the License, or (at your option) any later
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version.
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Sortix is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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details.
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You should have received a copy of the GNU General Public License along
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with Sortix. If not, see <http://www.gnu.org/licenses/>.
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memorymanagement.h
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Handles memory for the x86 family of architectures.
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******************************************************************************/
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#ifndef SORTIX_X86_FAMILY_MEMORYMANAGEMENT_H
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#define SORTIX_X86_FAMILY_MEMORYMANAGEMENT_H
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namespace Sortix
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{
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struct PML
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{
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addr_t entry[4096 / sizeof(addr_t)];
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};
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namespace Memory
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{
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const addr_t PML_PRESENT = (1<<0);
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const addr_t PML_WRITABLE = (1<<1);
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const addr_t PML_USERSPACE = (1<<2);
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const addr_t PML_WRTHROUGH = (1<<3);
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const addr_t PML_NOCACHE = (1<<4);
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const addr_t PML_PAT = (1<<7);
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const addr_t PML_AVAILABLE1 = (1<<9);
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const addr_t PML_AVAILABLE2 = (1<<10);
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const addr_t PML_AVAILABLE3 = (1<<11);
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const addr_t PML_FORK = PML_AVAILABLE1;
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const addr_t PML_FLAGS = (0xFFFUL); // Bits used for the flags.
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const addr_t PML_ADDRESS = (~0xFFFUL); // Bits used for the address.
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const addr_t PAT_UC = 0x00; // Uncacheable
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const addr_t PAT_WC = 0x01; // Write-Combine
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const addr_t PAT_WT = 0x04; // Writethrough
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const addr_t PAT_WP = 0x05; // Write-Protect
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const addr_t PAT_WB = 0x06; // Writeback
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const addr_t PAT_UCM = 0x07; // Uncacheable, overruled by MTRR.
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const addr_t PAT_NUM = 0x08;
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// Desired PAT-Register PA-Field Indexing (different from BIOS defaults)
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const addr_t PA[PAT_NUM] =
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{
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PAT_WB,
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PAT_WT,
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PAT_UCM,
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PAT_UC,
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PAT_WC,
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PAT_WP,
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0,
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0,
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};
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// Inverse function of the above.
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const addr_t PAINV[PAT_NUM] =
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{
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3, // UC
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4, // WC
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7, // No such
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8, // No such
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1, // WT
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5, // WP,
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0, // WB
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2, // UCM
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};
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static inline addr_t EncodePATAsPMLFlag(addr_t pat)
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{
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pat = PAINV[pat];
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addr_t result = 0;
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if ( pat & 0x1 ) { result |= PML_WRTHROUGH; }
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if ( pat & 0x2 ) { result |= PML_NOCACHE; }
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if ( pat & 0x4 ) { result |= PML_PAT; }
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return result;
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}
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bool MapKernelPAT(addr_t physical, addr_t mapto, addr_t mtype);
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bool MapUserPAT(addr_t physical, addr_t mapto, addr_t mtype);
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}
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}
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#ifdef PLATFORM_X86
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#include "../x86/memorymanagement.h"
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#endif
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#ifdef PLATFORM_X64
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#include "../x64/memorymanagement.h"
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#endif
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#endif
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