2b72262b4f
I hereby relicense all my work on Sortix under the ISC license as below. All Sortix contributions by other people are already under this license, are not substantial enough to be copyrightable, or have been removed. All imported code from other projects is compatible with this license. All GPL licensed code from other projects had previously been removed. Copyright 2011-2016 Jonas 'Sortie' Termansen and contributors. Permission to use, copy, modify, and distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
252 lines
10 KiB
C++
252 lines
10 KiB
C++
/*
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* Copyright (c) 2013, 2014, 2015, 2016 Jonas 'Sortie' Termansen.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* disk/ahci/registers.h
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* Driver for the Advanced Host Controller Interface.
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*/
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#ifndef SORTIX_DISK_AHCI_REGISTERS_H
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#define SORTIX_DISK_AHCI_REGISTERS_H
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#include <endian.h>
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#include <stdint.h>
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namespace Sortix {
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namespace AHCI {
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#define AHCI_COMMAND_HEADER_COUNT 32
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#if 1 /* ATA STUFF */
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#define ATA_STATUS_ERR (1 << 0) /* Error. */
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#define ATA_STATUS_DRQ (1 << 3) /* Data Request. */
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#define ATA_STATUS_DF (1 << 5) /* Device Fault. */
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#define ATA_STATUS_DRDY (1 << 6) /* Device Ready. */
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#define ATA_STATUS_BSY (1 << 7) /* Busy. */
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/** ATA Commands. */
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#define ATA_CMD_READ_DMA 0xC8 /**< READ DMA. */
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#define ATA_CMD_READ_DMA_EXT 0x25 /**< READ DMA EXT. */
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#define ATA_CMD_READ_SECTORS 0x20 /**< READ SECTORS. */
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#define ATA_CMD_READ_SECTORS_EXT 0x24 /**< READ SECTORS EXT. */
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#define ATA_CMD_WRITE_DMA 0xCA /**< WRITE DMA. */
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#define ATA_CMD_WRITE_DMA_EXT 0x35 /**< WRITE DMA EXT. */
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#define ATA_CMD_WRITE_SECTORS 0x30 /**< WRITE SECTORS. */
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#define ATA_CMD_WRITE_SECTORS_EXT 0x34 /**< WRITE SECTORS EXT. */
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#define ATA_CMD_PACKET 0xA0 /**< PACKET. */
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#define ATA_CMD_IDENTIFY_PACKET 0xA1 /**< IDENTIFY PACKET DEVICE. */
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#define ATA_CMD_FLUSH_CACHE 0xE7 /**< FLUSH CACHE. */
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#define ATA_CMD_FLUSH_CACHE_EXT 0xEA /**< FLUSH CACHE EXT. */
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#define ATA_CMD_IDENTIFY 0xEC /**< IDENTIFY DEVICE. */
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#endif
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struct fis
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{
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little_uint8_t dsfis[0x1C]; // DMA Setup FIS.
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little_uint8_t reserved1[0x04];
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little_uint8_t psfis[0x14]; // PIO Setup FIS.
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little_uint8_t reserved2[0x0C];
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little_uint8_t rfis[0x14]; // D2H Register FIS.
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little_uint8_t reserved3[0x04];
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little_uint8_t sdbfis[0x08]; // Set Device Bits FIS.
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little_uint8_t ufis[0x40]; // Unknown FIS.
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little_uint8_t reserved4[0x60];
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};
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/* TODO: Less blatantly copied from Kiwi: */
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struct command_header
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{
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/** DW0 - Description Information. */
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little_uint16_t dw0l;
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little_uint16_t prdtl;
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/** DW1 - Command Status. */
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little_uint32_t prdbc; /**< Physical Region Descriptor Byte Count. */
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/** DW2 - Command Table Base Address.
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* @note Bits 0-6 are reserved, must be 0. */
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little_uint32_t ctba; /**< Command Table Descriptor Base Address. */
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/** DW3 - Command Table Base Address Upper. */
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little_uint32_t ctbau; /**< Command Table Descriptor Base Address Upper 32-bits. */
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/** DW4-7 - Reserved. */
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little_uint32_t reserved2[4];
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};
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static const uint32_t COMMAND_HEADER_DW0_WRITE = 1 << 6;
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/* TODO: Less blatantly copied from Kiwi: */
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struct prd
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{
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/** DW0 - Data Base Address. */
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little_uint32_t dba;
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/** DW1 - Data Base Address Upper. */
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little_uint32_t dbau;
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/** DW2 - Reserved */
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little_uint32_t reserved1;
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/** DW3 - Description Information. */
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/* dw3 bits 0-21: data byte count */
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/* dw3 bits 22-30: reserved */
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/* dw3 bits 31-31: interrupt on completion */
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little_uint32_t dw3;
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};
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/* TODO: Less blatantly copied from Kiwi: */
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struct command_table
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{
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/** Command FIS - Host to Device. */
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struct
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{
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little_uint8_t type; /**< FIS Type (0x27). */
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/*little_*/uint8_t pm_port : 4; /**< Port Multiplier Port. */
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/*little_*/uint8_t reserved1 : 3; /**< Reserved. */
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/*little_*/uint8_t c_bit : 1; /**< C bit. */
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little_uint8_t command; /**< ATA Command. */
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little_uint8_t features_0_7; /**< Features (bits 0-7). */
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little_uint8_t lba_0_7; /**< LBA (bits 0-7). */
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little_uint8_t lba_8_15; /**< LBA (bits 8-15). */
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little_uint8_t lba_16_23; /**< LBA (bits 16-23). */
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little_uint8_t device; /**< Device (bits 24-27 for LBA28). */
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little_uint8_t lba_24_31; /**< LBA48 (bits 24-31). */
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little_uint8_t lba_32_39; /**< LBA48 (bits 32-39). */
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little_uint8_t lba_40_47; /**< LBA48 (bits 40-47). */
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little_uint8_t features_8_15; /**< Features (bits 8-15). */
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little_uint8_t count_0_7; /**< Sector Count (bits 0-7). */
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little_uint8_t count_8_15; /**< Sector Count (bits 8-15). */
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little_uint8_t icc; /**< Isochronous Command Completion. */
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little_uint8_t control; /**< Device Control. */
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little_uint32_t reserved2; /**< Reserved. */
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little_uint8_t padding[0x2C]; /**< Padding to 64 bytes. */
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} cfis;
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little_uint8_t acmd[0x10]; /**< ATAPI Command (12 or 16 bytes). */
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little_uint8_t reserved[0x30]; /**< Reserved. */
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};
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struct port_regs
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{
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little_uint32_t pxclb;
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little_uint32_t pxclbu;
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little_uint32_t pxfb;
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little_uint32_t pxfbu;
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little_uint32_t pxis;
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little_uint32_t pxie;
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little_uint32_t pxcmd;
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little_uint32_t reserved0;
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little_uint32_t pxtfd;
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little_uint32_t pxsig;
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little_uint32_t pxssts;
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little_uint32_t pxsctl;
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little_uint32_t pxserr;
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little_uint32_t pxsact;
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little_uint32_t pxci;
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little_uint32_t pxsntf;
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little_uint32_t pxfbs;
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little_uint32_t preserved1[15];
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};
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/** Bits in the Port x Interrupt Enable register. */
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#define PXIE_DHRE (1 << 0) /**< Device to Host Register Enable. */
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#define PXIE_PSE (1 << 1) /**< PIO Setup FIS Enable. */
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#define PXIE_DSE (1 << 2) /**< DMA Setup FIS Enable. */
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#define PXIE_SDBE (1 << 3) /**< Set Device Bits Enable. */
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#define PXIE_UFE (1 << 4) /**< Unknown FIS Enable. */
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#define PXIE_DPE (1 << 5) /**< Descriptor Processed Enable. */
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#define PXIE_PCE (1 << 6) /**< Port Connect Change Enable. */
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#define PXIE_DMPE (1 << 7) /**< Device Mechanical Presence Enable. */
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#define PXIE_PRCE (1 << 22) /**< PhyRdy Change Enable. */
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#define PXIE_IPME (1 << 23) /**< Incorrect Port Multiplier Enable. */
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#define PXIE_OFE (1 << 24) /**< Overflow Enable. */
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#define PXIE_INFE (1 << 26) /**< Interface Non-Fatal Error Enable. */
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#define PXIE_IFE (1 << 27) /**< Interface Fatal Error Enable. */
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#define PXIE_HBDE (1 << 28) /**< Host Bus Data Error Enable. */
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#define PXIE_HBFE (1 << 29) /**< Host Bus Fatal Error Enable. */
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#define PXIE_TFEE (1 << 30) /**< Task File Error Enable. */
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#define PXIE_CPDE (1 << 31) /**< Cold Port Detect Enable. */
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#define PORT_INTR_ERROR \
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(PXIE_UFE | PXIE_PCE | PXIE_PRCE | PXIE_IPME | \
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PXIE_OFE | PXIE_INFE | PXIE_IFE | PXIE_HBDE | \
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PXIE_HBFE | PXIE_TFEE)
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static const uint32_t PXCMD_ST = 1 << 0; /* 0x00000001 */
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static const uint32_t PXCMD_SUD = 1 << 1; /* 0x00000002 */
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static const uint32_t PXCMD_POD = 1 << 2; /* 0x00000004 */
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static const uint32_t PXCMD_CLO = 1 << 3; /* 0x00000008 */
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static const uint32_t PXCMD_FRE = 1 << 4; /* 0x00000010 */
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static inline uint32_t PXCMD_CSS(uint32_t val) { return (val >> 8) % 32; }
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static const uint32_t PXCMD_MPSS = 1 << 13; /* 0x00002000 */
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static const uint32_t PXCMD_FR = 1 << 14; /* 0x00004000 */
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static const uint32_t PXCMD_CR = 1 << 15; /* 0x00008000 */
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static const uint32_t PXCMD_CPS = 1 << 16; /* 0x00010000 */
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static const uint32_t PXCMD_PMA = 1 << 17; /* 0x00020000 */
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static const uint32_t PXCMD_HPCP = 1 << 18; /* 0x00040000 */
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static const uint32_t PXCMD_MPSP = 1 << 19; /* 0x00080000 */
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static const uint32_t PXCMD_CPD = 1 << 20; /* 0x00100000 */
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static const uint32_t PXCMD_ESP = 1 << 21; /* 0x00200000 */
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static const uint32_t PXCMD_FBSCP = 1 << 22; /* 0x00400000 */
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static const uint32_t PXCMD_APSTE = 1 << 23; /* 0x00800000 */
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static const uint32_t PXCMD_ATAPI = 1 << 24; /* 0x01000000 */
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static const uint32_t PXCMD_DLAE = 1 << 25; /* 0x02000000 */
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static const uint32_t PXCMD_ALPE = 1 << 26; /* 0x04000000 */
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static const uint32_t PXCMD_ASP = 1 << 27; /* 0x08000000 */
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static inline uint32_t PXCMD_ICC(uint32_t val) { return (val >> 28) % 16; }
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struct hba_regs
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{
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little_uint32_t cap;
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little_uint32_t ghc;
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little_uint32_t is;
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little_uint32_t pi;
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little_uint32_t vs;
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little_uint32_t ccc_ctl;
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little_uint32_t ccc_ports;
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little_uint32_t em_loc;
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little_uint32_t em_ctl;
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little_uint32_t cap2;
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little_uint32_t bohc;
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little_uint32_t reserved0[53];
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struct port_regs ports[32];
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};
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static_assert(sizeof(struct hba_regs) == 0x1100,
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"sizeof(struct hba_regs) == 0x1100");
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static const uint32_t CAP_S64A = 1U << 31;
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static const uint32_t CAP_SNCQ = 1U << 30;
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static const uint32_t CAP_SSNTF = 1U << 29;
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static const uint32_t CAP_SMPS = 1U << 28;
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static const uint32_t CAP_SSS = 1U << 27;
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static const uint32_t CAP_SALP = 1U << 26;
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static const uint32_t CAP_SAL = 1U << 25;
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static const uint32_t CAP_SCLO = 1U << 24;
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static inline uint32_t CAP_ISS(uint32_t val) { return (val >> 20) % 16; }
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static const uint32_t CAP_SAM = 1U << 18;
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static const uint32_t CAP_SPM = 1U << 17;
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static const uint32_t CAP_FBSS = 1U << 16;
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static const uint32_t CAP_PMD = 1U << 15;
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static const uint32_t CAP_SSC = 1U << 14;
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static const uint32_t CAP_PSC = 1U << 13;
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static inline uint32_t CAP_NCS(uint32_t val) { return (val >> 8) % 32 + 1; }
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static const uint32_t CAP_CCCS = 1U << 7;
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static const uint32_t CAP_EMS = 1U << 6;
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static const uint32_t CAP_SXS = 1U << 5;
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static inline uint32_t CAP_NP(uint32_t val) { return (val >> 0) % 32 + 1; }
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static const uint32_t GHC_AE = 1U << 31;
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static const uint32_t GHC_MRSM = 1U << 2;
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static const uint32_t GHC_IE = 1U << 1;
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static const uint32_t GHC_HR = 1U << 0;
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} // namespace AHCI
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} // namespace Sortix
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#endif
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