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Add ability to shift multiple steps in one instruction

This commit is contained in:
CrazyEttin 2022-09-11 19:44:53 +03:00
parent 4772222993
commit d4720f48c2
6 changed files with 42 additions and 22 deletions
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15
assembler.pas
View File

@ -331,17 +331,22 @@ begin
else if Elem [3] <> '' then ArgError else if Elem [3] <> '' then ArgError
else if Elem [4] <> '' then ArgError; else if Elem [4] <> '' then ArgError;
end end
else if Bin [BP] <= $50 then begin
if Elem [3] <> '' then ArgError
else if Elem [4] <> '' then ArgError;
end
else if Bin [BP] <= $b0 then begin else if Bin [BP] <= $b0 then begin
if Elem [4] <> '' then ArgError; if Elem [4] <> '' then ArgError;
end; end;
//Assemble the arguments //Assemble the arguments
//Shifts //Shifts
if Bin [BP] >= $20 then if Bin [BP] <= $50 then OneArgReg (2); if Bin [BP] >= $20 then if Bin [BP] <= $50 then begin
//First argument
OneArgReg (2);
//Second argument
if CompareText (Elem [3], '1') = 0 then Bin [BP] := Bin [BP] + 1
else if CompareText (Elem [3], '2') = 0 then Bin [BP] := Bin [BP] + 2
else if CompareText (Elem [3], '3') = 0 then Bin [BP] := Bin [BP] + 3
else if CompareText (Elem [3], '4') = 0 then Bin [BP] := Bin [BP] + 0
else ArgError;
end;
//Logical operations //Logical operations
if Bin [BP] >= $60 then if Bin [BP] <= $90 then TwoArgRegs; if Bin [BP] >= $60 then if Bin [BP] <= $90 then TwoArgRegs;
//Load //Load

8
disassembler.pas
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@ -111,7 +111,13 @@ begin
write (Opcodes [Op]); write (Opcodes [Op]);
if Op = $b then writeln (IntToHex (Addr, 1), ', R', X) if Op = $b then writeln (IntToHex (Addr, 1), ', R', X)
else begin else begin
if Op >= 2 then write ('R', X); if Op >= 2 then begin
write ('R', X);
if Op <= 5 then begin
if Y = 0 then write (', 4')
else write (', ', Y);
end;
end;
if Op >= 6 then if Op <= 9 then write (', R', Y); if Op >= 6 then if Op <= 9 then write (', R', Y);
if OP >= $c then write (', R', Y); if OP >= $c then write (', R', Y);
if Op >= $a then begin if Op >= $a then begin

20
emulator.pas
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@ -374,13 +374,25 @@ begin
RP := RP + 1; RP := RP + 1;
end end
//Shl //Shl
else if Op = 2 then R [X] := R [X] shl 1 else if Op = 2 then begin
if Y = 0 then R [X] := R [X] shl 4
else R [X] := R [X] shl Y;
end
//Shr //Shr
else if Op = 3 then R [X] := R [X] shr 1 else if Op = 3 then begin
if Y = 0 then R [X] := R [X] shr 4
else R [X] := R [X] shr Y;
end
//Rol //Rol
else if Op = 4 then R [X] := RolByte (R [X]) else if Op = 4 then begin
if Y = 0 then R [X] := RolByte (R [X], 4)
else R [X] := RolByte (R [X], Y);
end
//Ror //Ror
else if Op = 5 then R [X] := RorByte (R [X]) else if Op = 5 then begin
if Y = 0 then R [X] := RorByte (R [X], 4)
else R [X] := RorByte (R [X], Y);
end
//Nand //Nand
else if Op = 6 then R [X] := not (R [X] and R [Y]) else if Op = 6 then R [X] := not (R [X] and R [Y])
//And //And

5
examples/ascii.asm
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@ -16,10 +16,7 @@
;Convert and print the high nibble ;Convert and print the high nibble
;Convert ;Convert
ror r0 ror r0, 4
ror r0
ror r0
ror r0
cleq r0, r0, n2hex cleq r0, r0, n2hex
;Print ;Print
store ffff, r0 store ffff, r0

4
examples/echo.asm
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@ -228,11 +228,11 @@ sumlop: xor r1, r1
xor r1, r1 xor r1, r1
xor r1, r2 xor r1, r2
;Shift the carry ;Shift the carry
shl r2 shl r2, 1
;Check for and store overflow if any ;Check for and store overflow if any
;Check ;Check
rol r1 rol r1, 1
breq r1, r2, nvrflw breq r1, r2, nvrflw
;Store ;Store
load r1, #1 load r1, #1

12
readme.md
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@ -1,5 +1,5 @@
Thingamajig v1.0 Thingamajig v1.1-dev
================ ====================
Thingamajig is a RISC/MISC homebrew computer architecture. Its git Thingamajig is a RISC/MISC homebrew computer architecture. Its git
repository can be found at repository can be found at
@ -37,10 +37,10 @@ instruction pointer is incremented before being accessed or modified.
0 HALT 0 HALT
1 RET IP = *RP; RP += 2 1 RET IP = *RP; RP += 2
2 SHL RX RX <<= 1 Logical shifts 2 SHL RX, N RX <<= N (logical) Shifts of 1-4 steps,
3 SHR RX RX >>= 1 3 SHR RX, N RX >>= N (logical) with 4 encoded as 0
4 ROL RX RX <<= 1 Rotating shifts 4 ROL RX, N RX <<= N (rotating) in machine code.
5 ROR RX RX >>= 1 5 ROR RX, N RX >>= N (rotating)
6 NAND RX, RY RX = ~(RX & RY) 6 NAND RX, RY RX = ~(RX & RY)
7 AND RX, RY RX &= RY 7 AND RX, RY RX &= RY