274 lines
8.1 KiB
C++
274 lines
8.1 KiB
C++
/*******************************************************************************
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COPYRIGHT(C) JONAS 'SORTIE' TERMANSEN 2011, 2012.
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This file is part of Sortix.
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Sortix is free software: you can redistribute it and/or modify it under the
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terms of the GNU General Public License as published by the Free Software
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Foundation, either version 3 of the License, or (at your option) any later
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version.
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Sortix is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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details.
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You should have received a copy of the GNU General Public License along with
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Sortix. If not, see <http://www.gnu.org/licenses/>.
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interrupt.cpp
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High level interrupt service routines and interrupt request handlers.
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*******************************************************************************/
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#include <sortix/kernel/platform.h>
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#include "x86-family/idt.h"
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#include "interrupt.h"
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#include "process.h" // Hack for SIGSEGV
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#include "sound.h" // Hack for SIGSEGV
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#include "thread.h" // HACK FOR SIGSEGV
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#include "syscall.h" // HACK FOR SIGSEGV
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#include "scheduler.h" // HACK FOR SIGSEGV
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namespace Sortix {
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void SysExit(int status); // HACK
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namespace Interrupt {
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const uint16_t PIC_MASTER = 0x20;
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const uint16_t PIC_SLAVE = 0xA0;
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const uint16_t PIC_COMMAND = 0x00;
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const uint16_t PIC_DATA = 0x01;
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const uint8_t PIC_CMD_ENDINTR = 0x20;
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const uint8_t PIC_ICW1_ICW4 = 0x01; // ICW4 (not) needed
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const uint8_t PIC_ICW1_SINGLE = 0x02; // Single (cascade) mode
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const uint8_t PIC_ICW1_INTERVAL4 = 0x04; // Call address interval 4 (8)
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const uint8_t PIC_ICW1_LEVEL = 0x08; // Level triggered (edge) mode
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const uint8_t PIC_CMD_INIT = 0x10;
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const uint8_t PIC_MODE_8086 = 0x01; // 8086/88 (MCS-80/85) mode
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const uint8_t PIC_MODE_AUTO = 0x02; // Auto (normal) EOI
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const uint8_t PIC_MODE_BUF_SLAVE = 0x08; // Buffered mode/slave
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const uint8_t PIC_MODE_BUF_MASTER = 0x0C; // Buffered mode/master
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const uint8_t PIC_MODE_SFNM = 0x10; // Special fully nested (not)
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const bool DEBUG_EXCEPTION = false;
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const bool DEBUG_IRQ = false;
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bool initialized;
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const size_t NUM_KNOWN_EXCEPTIONS = 20;
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const char* exceptions[] =
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{
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"Divide by zero",
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"Debug",
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"Non maskable interrupt",
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"Breakpoint",
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"Into detected overflow",
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"Out of bounds",
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"Invalid opcode",
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"No coprocessor",
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"Double fault",
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"Coprocessor segment overrun",
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"Bad TSS",
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"Segment not present",
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"Stack fault",
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"General protection fault",
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"Page fault",
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"Unknown interrupt",
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"Coprocessor fault",
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"Alignment check",
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"Machine check",
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"SIMD Floating-Point",
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};
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const unsigned NUM_INTERRUPTS = 256UL;
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Handler interrupthandlers[NUM_INTERRUPTS];
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void* interrupthandlerptr[NUM_INTERRUPTS];
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void Init()
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{
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initialized = false;
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IDT::Init();
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for ( unsigned i = 0; i < NUM_INTERRUPTS; i++ )
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{
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interrupthandlers[i] = NULL;
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interrupthandlerptr[i] = NULL;
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RegisterRawHandler(i, interrupt_handler_null, false);
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}
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// Remap the IRQ table on the PICs.
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uint8_t mastermask = 0;
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uint8_t slavemask = 0;
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CPU::OutPortB(PIC_MASTER + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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CPU::OutPortB(PIC_SLAVE + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, IRQ0);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, IRQ8);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, 0x04); // Slave PIC at IRQ2
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, 0x02); // Cascade Identity
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CPU::OutPortB(PIC_MASTER + PIC_DATA, PIC_MODE_8086);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, PIC_MODE_8086);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, mastermask);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, slavemask);
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RegisterRawHandler(0, isr0, false);
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RegisterRawHandler(1, isr1, false);
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RegisterRawHandler(2, isr2, false);
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RegisterRawHandler(3, isr3, false);
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RegisterRawHandler(4, isr4, false);
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RegisterRawHandler(5, isr5, false);
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RegisterRawHandler(6, isr6, false);
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RegisterRawHandler(7, isr7, false);
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RegisterRawHandler(8, isr8, false);
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RegisterRawHandler(9, isr9, false);
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RegisterRawHandler(10, isr10, false);
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RegisterRawHandler(11, isr11, false);
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RegisterRawHandler(12, isr12, false);
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RegisterRawHandler(13, isr13, false);
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RegisterRawHandler(14, isr14, false);
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RegisterRawHandler(15, isr15, false);
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RegisterRawHandler(16, isr16, false);
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RegisterRawHandler(17, isr17, false);
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RegisterRawHandler(18, isr18, false);
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RegisterRawHandler(19, isr19, false);
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RegisterRawHandler(20, isr20, false);
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RegisterRawHandler(21, isr21, false);
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RegisterRawHandler(22, isr22, false);
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RegisterRawHandler(23, isr23, false);
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RegisterRawHandler(24, isr24, false);
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RegisterRawHandler(25, isr25, false);
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RegisterRawHandler(26, isr26, false);
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RegisterRawHandler(27, isr27, false);
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RegisterRawHandler(28, isr28, false);
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RegisterRawHandler(29, isr29, false);
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RegisterRawHandler(30, isr30, false);
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RegisterRawHandler(31, isr31, false);
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RegisterRawHandler(32, irq0, false);
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RegisterRawHandler(33, irq1, false);
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RegisterRawHandler(34, irq2, false);
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RegisterRawHandler(35, irq3, false);
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RegisterRawHandler(36, irq4, false);
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RegisterRawHandler(37, irq5, false);
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RegisterRawHandler(38, irq6, false);
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RegisterRawHandler(39, irq7, false);
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RegisterRawHandler(40, irq8, false);
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RegisterRawHandler(41, irq9, false);
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RegisterRawHandler(42, irq10, false);
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RegisterRawHandler(43, irq11, false);
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RegisterRawHandler(44, irq12, false);
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RegisterRawHandler(45, irq13, false);
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RegisterRawHandler(46, irq14, false);
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RegisterRawHandler(47, irq15, false);
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// TODO: Let the syscall.cpp code register this.
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RegisterRawHandler(128, syscall_handler, true);
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IDT::Flush();
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initialized = true;
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Interrupt::Enable();
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}
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void RegisterHandler(unsigned n, Interrupt::Handler handler, void* user)
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{
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interrupthandlers[n] = handler;
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interrupthandlerptr[n] = user;
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}
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// TODO: This function contains magic IDT-related values!
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void RegisterRawHandler(unsigned index, RawHandler handler, bool userspace)
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{
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addr_t handlerentry = (addr_t) handler;
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uint16_t sel = 0x08;
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uint8_t flags = 0x8E;
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if ( userspace ) { flags |= 0x60; }
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IDT::SetGate(index, handlerentry, sel, flags);
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if ( initialized ) { IDT::Flush(); }
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}
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void CrashHandler(CPU::InterruptRegisters* regs)
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{
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const char* message = ( regs->int_no < NUM_KNOWN_EXCEPTIONS )
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? exceptions[regs->int_no] : "Unknown";
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if ( DEBUG_EXCEPTION ) { regs->LogRegisters(); Log::Print("\n"); }
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#ifdef PLATFORM_X64
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addr_t ip = regs->rip;
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#else
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addr_t ip = regs->eip;
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#endif
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// Halt and catch fire if we are the kernel.
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unsigned codemode = regs->cs & 0x3U;
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if ( codemode == 0 )
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{
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PanicF("Unhandled CPU Exception id %zu '%s' at ip=0x%zx "
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"(cr2=0x%p, err_code=0x%p)", regs->int_no, message,
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ip, regs->cr2, regs->err_code);
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}
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Log::Print("The current program has crashed and was terminated:\n");
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Log::PrintF("%s exception at ip=0x%zx (cr2=0x%p, err_code=0x%p)\n",
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message, ip, regs->cr2, regs->err_code);
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Sound::Mute();
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CurrentProcess()->Exit(139);
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Scheduler::ProcessTerminated(regs);
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}
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void ISRHandler(Sortix::CPU::InterruptRegisters* regs)
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{
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if ( regs->int_no < 32 )
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{
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CrashHandler(regs);
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return;
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}
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if ( interrupthandlers[regs->int_no] != NULL )
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{
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void* user = interrupthandlerptr[regs->int_no];
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interrupthandlers[regs->int_no](regs, user);
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}
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}
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void IRQHandler(Sortix::CPU::InterruptRegisters* regs)
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{
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// TODO: IRQ 7 and 15 might be spurious and might need to be ignored.
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// See http://wiki.osdev.org/PIC for details (section Spurious IRQs).
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if ( regs->int_no == 32 + 7 || regs->int_no == 32 + 15 ) { return; }
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if ( DEBUG_IRQ )
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{
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Log::PrintF("IRQ%u ", regs->int_no-32);
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regs->LogRegisters();
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Log::Print("\n");
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}
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unsigned int_no = regs->int_no;
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// Send an EOI (end of interrupt) signal to the PICs.
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if ( IRQ8 <= int_no ) { CPU::OutPortB(PIC_SLAVE, PIC_CMD_ENDINTR); }
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CPU::OutPortB(PIC_MASTER, PIC_CMD_ENDINTR);
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if ( interrupthandlers[int_no] )
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{
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void* user = interrupthandlerptr[int_no];
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interrupthandlers[int_no](regs, user);
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}
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}
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extern "C" void interrupt_handler(Sortix::CPU::InterruptRegisters* regs)
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{
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size_t int_no = regs->int_no;
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if ( 32 <= int_no && int_no < 48 ) { IRQHandler(regs); }
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else { ISRHandler(regs); }
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}
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} // namespace Interrupt
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} // namespace Sortix
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