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Support changed store encoding and load immediate in thingamajig_disasm.py

This commit is contained in:
Juhani Krekelä 2022-08-27 19:25:42 +03:00
parent bbb5b4b35f
commit 0fc5da3483
1 changed files with 33 additions and 23 deletions
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56
thingamajig_disasm.py
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@ -1,32 +1,32 @@
#!/usr/bin/env python
from collections import namedtuple
Opcode = namedtuple('Opcode', ('mnemonic', 'rx', 'ry', 'addr'))
Opcode = namedtuple('Opcode', ('mnemonic', 'rx', 'ry', 'addr', 'immediate'))
opcodes = [
Opcode('halt', rx=False, ry=False, addr=False),
Opcode('ret', rx=False, ry=False, addr=False),
Opcode('halt', rx=False, ry=False, addr=False, immediate=False),
Opcode('ret', rx=False, ry=False, addr=False, immediate=False),
Opcode('shl', rx=True, ry=False, addr=False),
Opcode('shr', rx=True, ry=False, addr=False),
Opcode('rol', rx=True, ry=False, addr=False),
Opcode('ror', rx=True, ry=False, addr=False),
Opcode('shl', rx=True, ry=False, addr=False, immediate=False),
Opcode('shr', rx=True, ry=False, addr=False, immediate=False),
Opcode('rol', rx=True, ry=False, addr=False, immediate=False),
Opcode('ror', rx=True, ry=False, addr=False, immediate=False),
Opcode('nand', rx=True, ry=True, addr=False),
Opcode('and', rx=True, ry=True, addr=False),
Opcode('or', rx=True, ry=True, addr=False),
Opcode('xor', rx=True, ry=True, addr=False),
Opcode('nand', rx=True, ry=True, addr=False, immediate=False),
Opcode('and', rx=True, ry=True, addr=False, immediate=False),
Opcode('or', rx=True, ry=True, addr=False, immediate=False),
Opcode('xor', rx=True, ry=True, addr=False, immediate=False),
Opcode('load', rx=True, ry=False, addr=True),
Opcode('store', rx=True, ry=False, addr=True),
Opcode('load', rx=True, ry=False, addr=True, immediate=True),
Opcode('store', rx=False, ry=True, addr=True, immediate=False),
Opcode('breq', rx=True, ry=True, addr=True),
Opcode('brneq', rx=True, ry=True, addr=True),
Opcode('cleq', rx=True, ry=True, addr=True),
Opcode('clneq', rx=True, ry=True, addr=True),
Opcode('breq', rx=True, ry=True, addr=True, immediate=False),
Opcode('brneq', rx=True, ry=True, addr=True, immediate=False),
Opcode('cleq', rx=True, ry=True, addr=True, immediate=False),
Opcode('clneq', rx=True, ry=True, addr=True, immediate=False),
]
Instruction = namedtuple('Instruction', ['opcode', 'rx', 'ry', 'addr'])
Instruction = namedtuple('Instruction', ['opcode', 'rx', 'ry', 'addr', 'immediate'])
Data = namedtuple('Data', ['byte'])
Statement = namedtuple('Statement', ['addr', 'raw', 'contents'])
@ -42,24 +42,32 @@ def segment(binary, origin):
rx = (byte >> 2) & 3
ry = byte & 3
immediate = opcodes[opcode].immediate and ry == 3
valid = True
if not opcodes[opcode].rx and rx != 0: valid = False
if not opcodes[opcode].ry and ry != 0: valid = False
if opcodes[opcode].addr and ip + 2 >= len(binary): valid = False
if not opcodes[opcode].ry and not immediate and ry != 0: valid = False
if opcodes[opcode].addr and not immediate and ip + 2 >= len(binary): valid = False
if immediate and ip + 1 >= len(binary): valid = False
if not valid:
raw = binary[ip:ip + 1]
statements.append(Statement(ip, raw, Data(byte)))
ip += 1
elif immediate:
raw = binary[ip:ip + 2]
instruction = Instruction(opcode, rx, ry, None, binary[ip + 1])
statements.append(Statement(ip, raw, instruction))
ip += 2
elif opcodes[opcode].addr:
raw = binary[ip:ip + 3]
addr = (binary[ip + 1] << 8) + binary[ip + 2]
instruction = Instruction(opcode, rx, ry, addr)
instruction = Instruction(opcode, rx, ry, addr, None)
statements.append(Statement(ip, raw, instruction))
ip += 3
else:
raw = binary[ip:ip + 1]
instruction = Instruction(opcode, rx, ry, None)
instruction = Instruction(opcode, rx, ry, None, None)
statements.append(Statement(ip, raw, instruction))
ip += 1
@ -76,7 +84,9 @@ def disasm(binary, origin = 0):
fields.append(f'r{contents.rx}')
if opcodes[contents.opcode].ry:
fields.append(f'r{contents.ry}')
if opcodes[contents.opcode].addr:
if contents.immediate is not None:
fields.append(f'#0x{contents.immediate:02x}')
elif opcodes[contents.opcode].addr:
fields.append(f'0x{contents.addr:04x}')
if mnemonic == 'store':