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Implement variable-width shifts

This commit is contained in:
Juhani Krekelä 2022-09-14 23:33:29 +03:00
parent e44b63dd15
commit b5e3cb7dff
2 changed files with 12 additions and 17 deletions
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16
calculator.asm
View File

@ -723,7 +723,7 @@ addByte:
; Calculate carries in r3 ; Calculate carries in r3
and r3, r0 and r3, r0
or r2, r3 ; Accumulate carry into carryout or r2, r3 ; Accumulate carry into carryout
shl r3 shl r3, 1
; Calculate sums in r0 ; Calculate sums in r0
xor r0, r1 xor r0, r1
; Copy carries into second addend ; Copy carries into second addend
@ -735,13 +735,8 @@ addByte:
brneq r1, r3, addByteLoop brneq r1, r3, addByteLoop
; Shift carryout, as we want carry from highest place = 1 ; Shift carryout, as we want carry from highest place = 1
shr r2 shr r2, 4
shr r2 shr r2, 3
shr r2
shr r2
shr r2
shr r2
shr r2
; Move carryout to r1 ; Move carryout to r1
; (We know r1 is already 0 since it's the loop condition) ; (We know r1 is already 0 since it's the loop condition)
@ -973,10 +968,7 @@ writehexByte:
or r2, r0 or r2, r0
; High nybble ; High nybble
shr r0 shr r0, 4
shr r0
shr r0
shr r0
cleq r0, r0, nybble2hex cleq r0, r0, nybble2hex
store ffff, r0 store ffff, r0

13
thingamajig_disasm.py
View File

@ -3,7 +3,7 @@ from collections import namedtuple
import enum import enum
class rfield(enum.Enum): class rfield(enum.Enum):
none, reg, imm_flag = range(3) none, reg, imm_flag, shift = range(4)
Opcode = namedtuple('Opcode', ('mnemonic', 'rx', 'ry', 'addr')) Opcode = namedtuple('Opcode', ('mnemonic', 'rx', 'ry', 'addr'))
@ -11,10 +11,10 @@ opcodes = [
Opcode('halt', rx=rfield.none, ry=rfield.none, addr=False), Opcode('halt', rx=rfield.none, ry=rfield.none, addr=False),
Opcode('ret', rx=rfield.none, ry=rfield.none, addr=False), Opcode('ret', rx=rfield.none, ry=rfield.none, addr=False),
Opcode('shl', rx=rfield.reg, ry=rfield.none, addr=False), Opcode('shl', rx=rfield.reg, ry=rfield.shift, addr=False),
Opcode('shr', rx=rfield.reg, ry=rfield.none, addr=False), Opcode('shr', rx=rfield.reg, ry=rfield.shift, addr=False),
Opcode('rol', rx=rfield.reg, ry=rfield.none, addr=False), Opcode('rol', rx=rfield.reg, ry=rfield.shift, addr=False),
Opcode('ror', rx=rfield.reg, ry=rfield.none, addr=False), Opcode('ror', rx=rfield.reg, ry=rfield.shift, addr=False),
Opcode('nand', rx=rfield.reg, ry=rfield.reg, addr=False), Opcode('nand', rx=rfield.reg, ry=rfield.reg, addr=False),
Opcode('and', rx=rfield.reg, ry=rfield.reg, addr=False), Opcode('and', rx=rfield.reg, ry=rfield.reg, addr=False),
@ -89,6 +89,9 @@ def disasm(binary, origin = 0):
fields.append(f'r{contents.rx}') fields.append(f'r{contents.rx}')
if opcodes[contents.opcode].ry == rfield.reg: if opcodes[contents.opcode].ry == rfield.reg:
fields.append(f'r{contents.ry}') fields.append(f'r{contents.ry}')
elif opcodes[contents.opcode].ry == rfield.shift:
shift = contents.ry if contents.ry != 0 else 4
fields.append(f'{shift}')
if contents.immediate is not None: if contents.immediate is not None:
fields.append(f'#{contents.immediate:02x}') fields.append(f'#{contents.immediate:02x}')
elif opcodes[contents.opcode].addr: elif opcodes[contents.opcode].addr: