Unify fields in ISA description in thingamajig_disasm.py
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@ -1,29 +1,33 @@
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#!/usr/bin/env python
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#!/usr/bin/env python
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from collections import namedtuple
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from collections import namedtuple
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import enum
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Opcode = namedtuple('Opcode', ('mnemonic', 'rx', 'ry', 'addr', 'immediate'))
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class rfield(enum.Enum):
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none, reg, imm_flag = range(3)
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Opcode = namedtuple('Opcode', ('mnemonic', 'rx', 'ry', 'addr'))
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opcodes = [
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opcodes = [
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Opcode('halt', rx=False, ry=False, addr=False, immediate=False),
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Opcode('halt', rx=rfield.none, ry=rfield.none, addr=False),
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Opcode('ret', rx=False, ry=False, addr=False, immediate=False),
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Opcode('ret', rx=rfield.none, ry=rfield.none, addr=False),
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Opcode('shl', rx=True, ry=False, addr=False, immediate=False),
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Opcode('shl', rx=rfield.reg, ry=rfield.none, addr=False),
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Opcode('shr', rx=True, ry=False, addr=False, immediate=False),
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Opcode('shr', rx=rfield.reg, ry=rfield.none, addr=False),
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Opcode('rol', rx=True, ry=False, addr=False, immediate=False),
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Opcode('rol', rx=rfield.reg, ry=rfield.none, addr=False),
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Opcode('ror', rx=True, ry=False, addr=False, immediate=False),
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Opcode('ror', rx=rfield.reg, ry=rfield.none, addr=False),
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Opcode('nand', rx=True, ry=True, addr=False, immediate=False),
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Opcode('nand', rx=rfield.reg, ry=rfield.reg, addr=False),
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Opcode('and', rx=True, ry=True, addr=False, immediate=False),
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Opcode('and', rx=rfield.reg, ry=rfield.reg, addr=False),
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Opcode('or', rx=True, ry=True, addr=False, immediate=False),
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Opcode('or', rx=rfield.reg, ry=rfield.reg, addr=False),
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Opcode('xor', rx=True, ry=True, addr=False, immediate=False),
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Opcode('xor', rx=rfield.reg, ry=rfield.reg, addr=False),
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Opcode('load', rx=True, ry=False, addr=True, immediate=True),
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Opcode('load', rx=rfield.reg, ry=rfield.imm_flag, addr=True),
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Opcode('store', rx=False, ry=True, addr=True, immediate=False),
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Opcode('store', rx=rfield.none, ry=rfield.reg, addr=True),
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Opcode('breq', rx=True, ry=True, addr=True, immediate=False),
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Opcode('breq', rx=rfield.reg, ry=rfield.reg, addr=True),
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Opcode('brneq', rx=True, ry=True, addr=True, immediate=False),
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Opcode('brneq', rx=rfield.reg, ry=rfield.reg, addr=True),
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Opcode('cleq', rx=True, ry=True, addr=True, immediate=False),
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Opcode('cleq', rx=rfield.reg, ry=rfield.reg, addr=True),
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Opcode('clneq', rx=True, ry=True, addr=True, immediate=False),
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Opcode('clneq', rx=rfield.reg, ry=rfield.reg, addr=True),
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]
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]
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Instruction = namedtuple('Instruction', ['opcode', 'rx', 'ry', 'addr', 'immediate'])
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Instruction = namedtuple('Instruction', ['opcode', 'rx', 'ry', 'addr', 'immediate'])
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@ -42,11 +46,12 @@ def segment(binary, origin):
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rx = (byte >> 2) & 3
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rx = (byte >> 2) & 3
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ry = byte & 3
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ry = byte & 3
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immediate = opcodes[opcode].immediate and ry == 3
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immediate = opcodes[opcode].ry == rfield.imm_flag and ry == 3
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valid = True
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valid = True
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if not opcodes[opcode].rx and rx != 0: valid = False
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if opcodes[opcode].rx == rfield.none and rx != 0: valid = False
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if not opcodes[opcode].ry and not immediate and ry != 0: valid = False
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if opcodes[opcode].ry == rfield.none and ry != 0: valid = False
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if opcodes[opcode].ry == rfield.imm_flag and ry not in (0, 3): valid = False
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if opcodes[opcode].addr and not immediate and ip + 2 >= len(binary): valid = False
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if opcodes[opcode].addr and not immediate and ip + 2 >= len(binary): valid = False
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if immediate and ip + 1 >= len(binary): valid = False
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if immediate and ip + 1 >= len(binary): valid = False
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@ -80,9 +85,9 @@ def disasm(binary, origin = 0):
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else:
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else:
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mnemonic = opcodes[contents.opcode].mnemonic
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mnemonic = opcodes[contents.opcode].mnemonic
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fields = []
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fields = []
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if opcodes[contents.opcode].rx:
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if opcodes[contents.opcode].rx == rfield.reg:
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fields.append(f'r{contents.rx}')
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fields.append(f'r{contents.rx}')
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if opcodes[contents.opcode].ry:
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if opcodes[contents.opcode].ry == rfield.reg:
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fields.append(f'r{contents.ry}')
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fields.append(f'r{contents.ry}')
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if contents.immediate is not None:
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if contents.immediate is not None:
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fields.append(f'#{contents.immediate:02x}')
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fields.append(f'#{contents.immediate:02x}')
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