Initial commit
This commit is contained in:
CrazyEttin
commit
75123a629a
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program Disassembler;
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uses Crt, Sysutils;
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var
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Op, Regs: 0 .. $f; //Opcode
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X, Y: 0 .. 3; //Register arguments
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Addr, IP, EP: word; //Address argument and instruction and end pointers
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Opcodes: array [0 .. $f] of string; //Opcodes in human readable form
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Bin: array [0 .. $ffef] of byte; //Program in binary form
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Prog: file of byte; //Program file
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begin
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//Populate the opcode array
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Opcodes [0] := 'HALT ';
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Opcodes [1] := 'RET ';
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Opcodes [2] := 'SHL ';
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Opcodes [3] := 'SHR ';
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Opcodes [4] := 'ROL ';
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Opcodes [5] := 'ROR ';
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Opcodes [6] := 'NAND ';
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Opcodes [7] := 'AND ';
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Opcodes [8] := 'OR ';
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Opcodes [9] := 'XOR ';
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Opcodes [$a] := 'LOAD ';
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Opcodes [$b] := 'STORE ';
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Opcodes [$c] := 'BREQ ';
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Opcodes [$d] := 'BRNEQ ';
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Opcodes [$e] := 'CLEQ ';
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Opcodes [$f] := 'CLNEQ ';
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//Initialise the pointer
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IP := 0;
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//Read a program file and check for errors
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if ParamCount <> 1 then begin
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writeln ('Usage: disassembler program');
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exit;
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end;
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{$i-}
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assign (Prog, ParamStr (1));
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reset (Prog);
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{$i+}
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if IOResult <> 0 then begin
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writeln ('Usage: disassembler program');
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exit;
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end;
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repeat
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read (Prog, Bin [IP]);
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IP := IP + 1;
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until (eof (Prog)) or (IP = $fff0);
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//Save the end point and reinitialise the instruction pointer
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EP := IP;
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IP := 0;
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//Begin the main loop
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repeat
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//Print the memory location
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if IP < $1000 then write (' ');
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if IP < $100 then write (' ');
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if IP < $10 then write (' ');
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write (IntToHex (IP, 1), ' ');
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//Fetch the instruction and increment the instruction pointer
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//Opcode
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Op := Bin [IP] and $f0 shr 4;
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//Register arguments
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Regs := Bin [IP] and $f;
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X := Bin [IP] and $c shr 2;
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Y := Bin [IP] and 3;
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IP := IP + 1;
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//Address argument
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if Op >= $a then begin
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Addr := Bin [IP];
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Addr := Addr shl 8;
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IP := IP + 1;
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Addr := Addr + Bin [IP];
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IP := IP - 1;
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end;
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//Print the data
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write (IntToHex (Op, 1), IntToHex (Regs, 1));
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if Op >= $a then write (IntToHex (Addr, 4)) else write (' ');
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write (' ');
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//Print the instruction
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write (Opcodes [Op]);
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if Op = $b then writeln (IntToHex (Addr, 1), ', R', X)
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else begin
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if Op >= 2 then if Op <> $b then write ('R', X);
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if Op >= 6 then if Op <= 9 then write (', R', Y);
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if OP >= $c then write (', R', Y);
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if Op >= $a then write (', ', IntToHex (Addr, 1));
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writeln ();
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end;
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until (IP >= EP);
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end.
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program Emulator;
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uses Crt;
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const
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IO = $ffff;
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var
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Halt: boolean; //Halt flag
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Op: 0 .. $f; //Opcode
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X, Y: 0 .. 3; //Register arguments
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Addr, IP, RP: word; //Address argument and instruction and return pointers
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R: array [0 .. 3] of byte; //General-purpose registers
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Mem: array [0 .. $ffef] of byte; //Memory
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Prog: file of byte; //Program file
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Ch: ansichar; //Character for input and output
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begin
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//Initialise the halt flag and the pointers
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Halt := false;
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IP := 0;
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RP := $fff0;
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//Read a program file and check for errors
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if ParamCount <> 1 then begin
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writeln ('Usage: emulator program');
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exit;
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end;
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{$i-}
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assign (Prog, ParamStr (1));
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reset (Prog);
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{$i+}
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if IOResult <> 0 then begin
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writeln ('Usage: emulator program');
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exit;
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end;
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repeat
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read (Prog, Mem [IP]);
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IP := IP + 1;
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until (eof (Prog)) or (IP = $fff0);
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//Reinitialise the instruction pointer
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IP := 0;
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//Begin the main loop
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while (Halt = false) do begin
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//Fetch the instruction and increment the instruction pointer
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//Opcode
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Op := Mem [IP] and $f0 shr 4;
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//Register arguments
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X := Mem [IP] and $c shr 2;
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Y := Mem [IP] and 3;
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IP := IP + 1;
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if IP > $ffef then break;
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//Address argument
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if Op >= $a then begin
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Addr := Mem [IP];
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Addr := Addr shl 8;
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IP := IP + 1;
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if IP > $ffef then break;
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Addr := Addr + Mem [IP];
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IP := IP + 1;
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if IP > $ffef then break;
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end;
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//Decode and execute the instruction
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//Halt
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if Op = 0 then Halt := true
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//Ret
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else if Op = 1 then begin
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IP := Mem [RP];
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RP := RP + 1;
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if RP > $fff0 then break;
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end
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//Shl
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else if Op = 2 then R [X] := R [X] shl 1
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//Shr
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else if Op = 3 then R [X] := R [X] shr 1
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//Rol
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else if Op = 4 then R [X] := RolByte (R [X])
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//Ror
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else if Op = 5 then R [X] := RorByte (R [X])
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//Nand
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else if Op = 6 then R [X] := not (R [X] and R [Y])
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//And
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else if Op = 7 then R [X] := R [X] and R [Y]
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//Or
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else if Op = 8 then R [X] := R [X] or R [Y]
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//Xor
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else if Op = 9 then R [X] := R [X] xor R [Y]
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//Load
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else if Op = $a then begin
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//Input
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if Addr = IO then begin
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Ch := ReadKey;
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write (Ch);
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R [X] := byte (Ch);
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end
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//Regular load
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else R [X] := Mem [Addr];
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end
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//Store
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else if Op = $b then begin
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//Output
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if Addr = IO then begin
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Ch := ansichar (R [X]);
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write (Ch);
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end
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//Regular store
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else Mem [Addr] := R [X];
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end
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//Breq
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else if Op = $c then begin
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if R [X] = R [Y] then IP := Addr;
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end
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//Brneq
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else if Op = $d then begin
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if R [X] <> R [Y] then IP := Addr;
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end
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//Cleq
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else if Op = $e then begin
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if R [X] = R [Y] then begin
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RP := RP - 1;
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if RP > $fff0 then break;
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Mem [RP] := IP;
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IP := Addr;
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if IP > $ffef then break;
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end;
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end
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//Clneq
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else if Op = $f then begin
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if R [X] <> R [Y] then begin
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RP := RP - 1;
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if RP > $fff0 then break;
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Mem [RP] := IP;
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IP := Addr;
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if IP > $ffef then break;
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end;
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end;
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//End the main loop
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end
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end.
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@ -0,0 +1,23 @@
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MIT License
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===========
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Copyright (c) 2022
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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@ -0,0 +1,58 @@
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Thingamajig
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===========
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Thingamajig is a RISC-y and MISC-y hobbyist instruction set
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architecture. Its git repository can be found at
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https://ahti.space/git/crazyettin/Thingamajig.
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Registers and Memory
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--------------------
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* 24-bit instruction register IR
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* 16-bit instruction and return pointers IP and RP
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* 8-bit general-purpose registers R0-R3
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* 8-bit memory addresses 0-FFFF
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Multi-byte values are big-endian. Memory addresses FFF0-FFFF are
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reserved for memory mapped devices. The instruction and return pointers
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should not have values higher than FFEF and FFF0 respectively to avoid
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the reserved addresses. The instruction and return pointers are
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initialised as 0 and FFF0 respectively; other registers and memory are
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unitialised.
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Memory-Mapped Devices
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---------------------
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Input (when read from) and output (when written to) are mapped to
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address FFFF. Arbitrary devices can be mapped to the other reserved
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addresses.
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Instructions
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------------
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Instructions without an address argument are 8-bit and those with one
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24-bit. The instruction pointer is incremented before being accessed or
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modified.
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0 HALT
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1 RET IP = *RP; RP += 1
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2 SHL RX RX <<= 1 Logical shifts
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3 SHR RX RX >>= 1
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4 ROL RX RX <<= 1 Rotating shifts
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5 ROR RX RX >>= 1
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6 NAND RX, RY RX = ~(RX & RY)
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7 AND RX, RY RX &= RY
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8 OR RX, RY RX |= RY
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9 XOR RX, RY RX ^= RY
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A LOAD RX, ADDR RX = *ADDR
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B STORE RX, ADDR *ADDR = RX Written as "STORE ADDR, RX" in
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assembly for the sake of
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consistency.
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C BREQ RX, RY, ADDR if (RX == RY) IP = ADDR
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D BRNEQ RX, RY, ADDR if (RX != RY) IP = ADDR
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E CLEQ RX, RY, ADDR if (RX == RY) {RP -= 1; *RP = IP; IP = ADDR}
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F CLNEQ RX, RY, ADDR if (RX != RY) {RP -= 1; *RP = IP; IP = ADDR}
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