Thingamajig

Thingamajig is a RISC-y and MISC-y hobbyist instruction set architecture. Its git repository can be found at https://ahti.space/git/crazyettin/Thingamajig.

Registers and Memory

• 24-bit instruction register IR
• 16-bit instruction and return pointers IP and RP
• 8-bit general-purpose registers R0-R3
• 8-bit memory addresses 0-FFFF

Multi-byte values are big-endian. Memory addresses FFF0-FFFF are reserved for memory mapped devices. The instruction and return pointers should not have values higher than FFEF and FFF0 respectively to avoid the reserved addresses. The instruction and return pointers are initialised as 0 and FFF0 respectively; other registers and memory are unitialised.

Memory-Mapped Devices

Input (when read from) and output (when written to) are mapped to address FFFF. Arbitrary devices can be mapped to the other reserved addresses.

Instructions

Instructions without an address argument are 8-bit and those with one 24-bit. The instruction pointer is incremented before being accessed or modified.

0 HALT 1 RET IP = *RP; RP += 1

2 SHL RX RX <<= 1 Logical shifts 3 SHR RX RX >>= 1 4 ROL RX RX <<= 1 Rotating shifts 5 ROR RX RX >>= 1

6 NAND RX, RY RX = ~(RX & RY) 7 AND RX, RY RX &= RY 8 OR RX, RY RX |= RY 9 XOR RX, RY RX ^= RY

A LOAD RX, ADDR RX = *ADDR B STORE RX, ADDR *ADDR = RX Written as "STORE ADDR, RX" in assembly for the sake of consistency.

C BREQ RX, RY, ADDR if (RX == RY) IP = ADDR D BRNEQ RX, RY, ADDR if (RX != RY) IP = ADDR E CLEQ RX, RY, ADDR if (RX == RY) {RP -= 1; *RP = IP; IP = ADDR} F CLNEQ RX, RY, ADDR if (RX != RY) {RP -= 1; *RP = IP; IP = ADDR}