59 lines
1.9 KiB
Markdown
59 lines
1.9 KiB
Markdown
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Thingamajig
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===========
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Thingamajig is a RISC-y and MISC-y hobbyist instruction set
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architecture. Its git repository can be found at
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https://ahti.space/git/crazyettin/Thingamajig.
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Registers and Memory
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--------------------
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* 24-bit instruction register IR
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* 16-bit instruction and return pointers IP and RP
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* 8-bit general-purpose registers R0-R3
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* 8-bit memory addresses 0-FFFF
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Multi-byte values are big-endian. Memory addresses FFF0-FFFF are
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reserved for memory mapped devices. The instruction and return pointers
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should not have values higher than FFEF and FFF0 respectively to avoid
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the reserved addresses. The instruction and return pointers are
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initialised as 0 and FFF0 respectively; other registers and memory are
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unitialised.
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Memory-Mapped Devices
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---------------------
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Input (when read from) and output (when written to) are mapped to
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address FFFF. Arbitrary devices can be mapped to the other reserved
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addresses.
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Instructions
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------------
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Instructions without an address argument are 8-bit and those with one
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24-bit. The instruction pointer is incremented before being accessed or
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modified.
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0 HALT
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1 RET IP = *RP; RP += 1
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2 SHL RX RX <<= 1 Logical shifts
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3 SHR RX RX >>= 1
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4 ROL RX RX <<= 1 Rotating shifts
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5 ROR RX RX >>= 1
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6 NAND RX, RY RX = ~(RX & RY)
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7 AND RX, RY RX &= RY
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8 OR RX, RY RX |= RY
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9 XOR RX, RY RX ^= RY
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A LOAD RX, ADDR RX = *ADDR
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B STORE RX, ADDR *ADDR = RX Written as "STORE ADDR, RX" in
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assembly for the sake of
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consistency.
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C BREQ RX, RY, ADDR if (RX == RY) IP = ADDR
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D BRNEQ RX, RY, ADDR if (RX != RY) IP = ADDR
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E CLEQ RX, RY, ADDR if (RX == RY) {RP -= 1; *RP = IP; IP = ADDR}
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F CLNEQ RX, RY, ADDR if (RX != RY) {RP -= 1; *RP = IP; IP = ADDR}
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